This invention relates generally to integrated circuits (IC) such as programmable logic devices (PLD), and more particularly the invention relates to a look-ahead macrocell register set/reset circuit having improved response time.
The programmable logic device, or PLD, is an integrated circuit which can be configured by the end user at his location to perform a specific unique logic function. Typically, the PLD comprises an array of programmable logic elements such as AND gates which combines the logistical advantages of standard fixed integrated circuits with the architectural flexibility of custom devices.
The combinatorial outputs of a PLD array can be connected through registers to an output driver and pad for registered configuration or directly to the output driver for combinatorial configuration to increase speed. Heretofore, much effort has been directed to optimizing the combinatorial propagation speed or propagation delay time, T.sub.pd, by providing the direct connection of the combinatorial logic to the output. However, the reset/set for the output is transmitted through the macrocell register without consideration for the reset/set times, T.sub.clear or T.sub.set, for the macrocell register. Thus, T.sub.clear is normally slower than T.sub.pd by at least 1 nanosecond and sometimes as much as 3 nanoseconds.